[1] G. Kestor, R. Gioiosa, O. Unsal, A. Cristal, and M. Valero. Hardware/software techniques for assisted execution runtime systems. In The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE), March 2012. [ bib ]
[2] V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, and M. Valero. A case for energy aware accounting in large scale computing facilities: Cost metrics and implications for processor design. In Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, June 2010. [ bib ]
[3] K. Kedzierski, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. Power and performance aware reconfigurable cache for cmps. In Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, June 2010. [ bib ]
[4] M. Paolieri, I. Bonesana, R. Gioiosa, and M. Valero. J-dse: Joint software and hardware design space exploration for application specific processors. In Third Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG), January 2010. [ bib ]
[5] V. Cakarevic, P. Radojkovic, R. Gioiosa, F. Cazorla, J. Verdu, A. Pajuelo, and M. Valero. Understanding the overhead of the spin-lock loop in CMT architectures . In "Workshop on the Interaction between Operating Systems and Computer Architecture" (WIOSCA), in conjunction with ISCA'08, Beijing, China, June 2008. [ bib ]
[6] V. Cakarevic, P. Radojkovic, R. Gioiosa, F. Cazorla, J. Verdu, A. Pajuelo, and M. Valero. Overhead of the spin-lock loop in UltraSPARC T2. the 5th HiPEAC Industrial Workshop, June 2008. [ bib ]
[7] José Carlos Sancho, Fabrizio Petrini, Kei Davis, Roberto Gioiosa, and Song Jiang. Current Practice and a Direction Forward in Checkpoint/Restart Implementations for Fault Tolerance. In First Workshop on System Management Tools for Large-Scale Parallel Systems, Denver, CO, April 2005. Available from http://www.c3.lanl.gov/~fabrizio/papers/survey-checkpoint.pdf. [ bib ]

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