[1] C. Luque, M. Moreto, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. CPU accounting for multicore processors. IEEE Transaction on Computers, February 2012. [ bib ]
[2] A. Morari, C. Boneti, F. Cazorla, R. Gioiosa, C. Cher, A. Buyuktosunoglu, P. Bose, and M. Valero. SMT malleability in IBM POWER5 and POWER6 processors. IEEE Transaction on Computers, To appear 2012. [ bib ]
[3] V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Cher, C. Isci, A. Buyuktosunoglu, and P. Bose. Characterizing power and temperature behavior of POWER6-based system. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems, September 2011. [ bib ]
[4] V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. A. Buyuktosunoglu, P. Bose, and M. Valero. A case for energy-aware accounting and billing in large-scale computing facilities cost metrics and design implications. IEEE Micro, May/June 2011. [ bib ]
[5] C. Luque, M. Moreto, F.J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. CPU accounting in CMP processors. Computer Architecture Letters, 2009. [ bib ]
[6] E. Betti, D.P. Bovet, M. Cesati, and R. Gioiosa. Hard real-time performances in multiprocessor embedded systems using ASMP-Linux. Operating System Support for Embedded Real-Time Applications special issue on Eurasip Journal on Embedded Systems, October 2007. [ bib ]

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